The present invention relates to the processing of semiconductor substrates. More particularly, the present invention relates to methods and apparatus for improving microloading while etching through a substrate's layer stack, including the metallization layer.
In semiconductor processing, devices such as component transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are typically etched from a metallization layer disposed above the substrate, may then be employed to couple the devices together to form the desired circuit.
To facilitate discussion, FIG. 1 illustrates a cross-section view of a layer stack 20, representing some of the layers formed during the fabrication of a typical semiconductor integrated circuit. Although a semiconductor integrated circuit (IC) is discussed herein to facilitate ease of understanding, the discussion herein also pertains to substrates employed to fabricate other electronic components, e.g., flat panel displays. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 20, there is shown a substrate 100. An oxide layer 102, typically comprising SiO.sub.2, may be formed above substrate 100. A barrier layer 104, typically formed of a titanium-containing layer such as Ti, TiW, TiN or other suitable barrier materials, may be disposed between oxide layer 102 and a subsequently deposited metallization layer 106. Barrier layer 104, when provided, functions to prevent the diffusion of silicon atoms from oxide layer 102 into the metallization layer.
Metallization layer 106 typically comprises copper, aluminum or one of the known aluminum alloys such as Al-Cu, Al-Si or Al-Cu-Si. When a layer contains aluminum or one of its alloys, that layer is referred to herein as the aluminum-containing layer. The remaining two layers of FIG. 1, i.e., an anti-reflective coating (ARC) layer 108 and an overlying photoresist (PR) layer 110, may then be formed atop metallization layer 106. The ARC layer 108, typically comprising another titanium-containing layer such as TiN or TiW, may help prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the metallization layer 106 and may, in some cases, inhibit hillock growth.
Photoresist layer 110 represents a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultra-violet rays. The layers of layer stack 20 are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To form the aforementioned metallic interconnect fines, a portion of the layers of the layer stack, including the metallization layer, e.g., metallization layer 106, may be etched using a suitable photoresist technique. By way of example, one such photoresist technique involves the patterning of photoresist layer 110 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of the metallization layer that are unprotected by the mask may then be etched away using an appropriate etching source gas, leaving behind metallization interconnect lines or features.
To achieve greater circuit density, modern IC circuits are scaled with increasingly narrower etch geometries. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased. By way of example, while a line width of approximately 0.8 microns (.mu.m) is considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) IC, 256 Mb DRAM IC's preferably employ interconnect lines as thin as 0.25 microns or even thinner.
As the feature sizes shrink, it becomes increasingly difficult to achieve even etch rates in different regions of the substrate. For example, the etch rate in the narrow spacings may different than that in the wider, open field regions. This phenomena, referred to herein as microloading, represents a significant challenge for process engineers. To elaborate, FIG. 2 illustrates a portion of layer stack 20 in which natural (or positive) microloading is observed. In layer stack 20, the etch rate through the narrow region 202(a) is slower than that of the open field region 204(a). Accordingly, the etch depth c in narrow region 204(a) is shallower than the etch depth b in open field region 204(a).
FIG. 3 illustrates the situation wherein reverse microloading is observed. Reverse microloading refers to the situation wherein the etch rate in the open field region 204(b) is slower than that in the narrow trench region 202(b). Accordingly, the etch depth b in open field region 204(b) is shallower than the etch depth c of narrow trench region 202(b). Mathematically speaking, the type and severity of microloading may be expressed as a microloading percentage calculated by the expression [(b-c)/b * 100] wherein b and c are the etch depths in the open field region and the narrow trench region respectively. If the microloading percentage is positive, the microloading is said to be natural (or positive). Conversely, if the microloading percentage is negative, the microloading is said to be reversed. In general, the larger the magnitude of the microloading percentage, the more severe the microloading problem.
Natural (or positive) microloading may be caused by many factors, e.g., inappropriate parameter settings, improper etch chemistries, narrow trench widths, and the like. It is observed that all things being equal, natural microloading tends to become more severe when trench widths fall below about 0.5microns, and especially when trench widths fall below about 0.35 microns. As a result of the etch rate variations associated with natural microloading, by the time metal etching is completed in areas having a slow etch rate (e.g., in the narrower spacings), overetching, i.e., the undue and inadvertent removal of materials from underlying layers, may already occur in areas having a higher etch rate (e.g., the open field regions).
In the past, process engineers respond to the presence of microloading by varying the etch parameters in a trial-and-error fashion until an acceptable level of microloading is achieved. By way of example, a process engineer may employ a large number of sample wafers to try out different etch pressures, increase or decrease the power settings, modify the etch chemistries, and/or the like, until one of the sample wafers meets the acceptable microloading threshold. As mentioned, however, the prior art process of remedying microloading is mostly by trial and error.
Although the prior art technique of addressing the microloading problem may eventually result in a set of process parameters that yields an acceptable level of microloading, there are significant disadvantages. For example, the trial-and-error approach necessarily involves a large number of attempts, which are costly both in terms of time and money. For some etchants/etch geometries combinations, it may not be possible to ever reach the satisfactory level of microloading irrespective of the settings of other process parameters. However, the process engineers may not necessarily have this knowledge until a large number of combinations have been attempted, which costs time and money.
Further, the process window may be limited with respect to certain process parameters, and it may not be possible to achieve a satisfactory level of microloading even if the highest parameter setting is employed. By way of example, the power supplies in most plasma processing systems have a finite range. A process engineer may find, after many trials and errors, that a satisfactory level of microloading is not possible even if he employs the highest power level available. However, the prior art trial-and-error approach makes it virtually impossible for a process engineer to find out these limitations unless a number of trial etches are first performed.
In view of the foregoing, there are desired improved techniques that permit process engineers to address the microloading issue in a cost-efficient and time-saving manner.